The electronics industry is approaching a limit to the variety of transistors that might be housed on the surface of a pc chip. So chipmakers want to accumulate quite than disappear.
Instead of compacting smaller and smaller transistors onto a single surface, the industry is trying to stack multiple surfaces of transistors and semiconductor elements – akin to converting a ranch house right into a high-rise. Such multilayered chips could process exponentially more data and perform far more complex functions than today's electronics.
However, a major hurdle is the platform on which the chips are built. Today, bulky silicon wafers serve because the fundamental framework on which high-quality, single-crystalline semiconductor elements grow. Any stackable chip would wish to contain a thick silicon “floor” as a part of each layer, slowing any communication between functional semiconductor layers.
Now MIT engineers have found a way around that hurdle with a multilayer chip design that doesn't require silicon wafer substrates and operates at temperatures low enough to preserve the underlying layer's circuitry.
In a study appears within the magazine today the team reports the brand new method for producing a multilayer chip with alternating layers of high-quality semiconductor material grown directly on top of one another.
The method allows engineers to construct high-performance transistors in addition to memory and logic elements on any crystalline surface – not only the bulky crystal framework of silicon wafers. Without these thick silicon substrates, multiple semiconductor layers could possibly be in additional direct contact, leading to raised and faster communication and computation between layers, the researchers say.
The researchers envision that this method could construct AI hardware in the shape of stacked chips for laptops or portable devices that may be as fast and powerful as today's supercomputers and will store massive amounts of knowledge on par with physical data centers.
“This breakthrough opens up enormous potential for the semiconductor industry and enables chip stacking without traditional limitations,” said study writer Jeehwan Kim, an associate professor of mechanical engineering at MIT. “This could lead on to orders of magnitude improvement in computing power for AI, logic and storage applications.”
MIT co-authors of the study include first writer Ki Seok Kim, Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng and Sangho Lee collaborators the Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea and the University of Texas at Dallas.
Seed bags
In 2023, Kim's group reported that they’d developed a way to grow high-quality semiconductor materials on amorphous surfaces, just like the varied topography of semiconductor circuits on finished chips. The material they grew was a style of 2D material often known as transition metal dichalcogenides (TMDs), which is taken into account a promising successor to silicon for making smaller, high-power transistors. Such 2D materials can maintain their semiconducting properties even at the dimensions of a single atom, while the performance of silicon drops sharply.
In their previous work, the team grew TMDs on silicon wafers with amorphous coatings in addition to on existing TMDs. To encourage atoms to rearrange themselves in high-quality single-crystalline form quite than random polycrystalline disorder, Kim and his colleagues first covered a silicon wafer with a really thin film, or “mask,” of silicon dioxide, which they patterned into tiny openings or pockets. They then flowed a gas manufactured from atoms over the mask and located that atoms became lodged within the pockets as “seeds.” The pockets restricted the seeds to growing in regular, single-crystal patterns.
However, at the moment the strategy only worked at around 900 degrees Celsius.
“You should grow this single-crystalline material at below 400 degrees Celsius, otherwise the circuit underneath is totally cooked and destroyed,” says Kim. “So our homework was to perform the same technique at temperatures below 400 degrees Celsius. If we could do this, the impact could be significant.”
Building up
In their recent work, Kim and his colleagues desired to refine their method for growing single-crystalline 2D materials at temperatures low enough to preserve all of the underlying circuitry. They found a surprisingly easy solution in metallurgy – the science and craft of metal production. When metallurgists pour molten metal right into a mold, the liquid slowly “nucleates,” or forms grains that grow and fuse right into a usually patterned crystal that hardens right into a solid shape. Metallurgists have discovered that this nucleation occurs most easily at the sides of a mold into which liquid metal is poured.
“It is thought that nucleation at the sides requires less energy – and warmth,” says Kim. “So we took this idea from metallurgy to make use of it for future AI hardware.”
The team desired to grow single-crystalline TMDs on a silicon wafer that was already made with transistor circuits. As with their previous work, they first covered the circuits with a mask manufactured from silicon dioxide. They then deposited “seeds” of TMD on the sides of every mask pocket and located that these edge seeds grew into single-crystalline material at temperatures as much as 380 degrees Celsius, in comparison with seeds that began growing in the center, further away the sides of every pocket, which required higher temperatures to form single crystal material.
The researchers went a step further and used the brand new method to create a multilayer chip with alternating layers of two different TMDs – molybdenum disulfide, a promising material candidate for making n-type transistors; and tungsten diselenide, a fabric that has the potential to be processed into p-type transistors. Both p-type and n-type transistors are the electronic constructing blocks to perform any logical operation. The team managed to grow each materials directly on top of one another in single-crystal form, without the necessity for intermediate silicon wafers. Kim says the strategy will effectively double the density of a chip's semiconductor elements, particularly metal-oxide-semiconductor (CMOS), which is a fundamental constructing block of contemporary logic circuits.
“A product realized with our technology just isn’t only a 3D logic chip, but additionally 3D memory and their combos,” says Kim. “With our growth-based 3D monolithic method, you may grow tens to a whole bunch of logic and memory layers directly on top of one another, and they’d have the opportunity to speak thoroughly.”
“Traditional 3D chips were fabricated with silicon wafers in between by drilling holes through the wafers – a process that limits the variety of stacked layers, vertical alignment resolution and yield,” adds lead writer Kiseok Kim. “Our growth-based method addresses all of those issues directly.”
To further commercialize her stackable chip design, Kim recently spun off an organization called FS2 (Future Semiconductor 2D Materials).
“So far we’re showing an idea for small device arrays,” he says. “The next step is scaling to show the operation of knowledgeable AI chip.”
This research is supported partially by the Samsung Advanced Institute of Technology and the US Air Force Office of Scientific Research.
