MIT researchers have developed a brand new manufacturing method that would enable the creation of more energy-efficient electronics by stacking multiple functional components on an existing circuit.
In traditional circuits, logic devices that perform calculations, reminiscent of transistors, and memory devices that store data are built as separate components, leading to data being transferred forwards and backwards between them, wasting energy.
This latest electronics integration platform allows scientists to fabricate transistors and memory devices in a compact stack on a semiconductor chip. This eliminates much of this wasted energy while increasing computing speed.
The key to this advancement is a newly developed material with unique properties and a more precise manufacturing approach that reduces the number of fabric defects. This allows researchers to create extremely small transistors with integrated memory that operate faster than state-of-the-art devices while consuming less power than similar transistors.
By improving the energy efficiency of electronic devices, this latest approach could help reduce the increasing power consumption of computations, especially for demanding applications reminiscent of generative AI, deep learning and computer vision tasks.
“We need to reduce the quantity of energy we use for AI and other data-centered computing in the long run since it is solely not sustainable. We will need latest technologies like this integration platform to proceed this progress,” says Yanjie Shao, a postdoctoral researcher at MIT and lead creator of two papers on these latest transistors.
The latest technique is described in two papers (certainly one of which was invited) presented on the IEEE International Electron Devices Meeting. Shao is joined within the work by senior authors Jesús del Alamo, the Donner Professor of Engineering in MIT's Department of Electrical Engineering and Computer Science (EECS); Dimitri Antoniadis, Ray and Maria Stata Professor of Electrical Engineering and Computer Science at MIT; in addition to others at MIT, the University of Waterloo and Samsung Electronics.
Turn the issue around
Standard CMOS (complementary metal-oxide semiconductor) chips traditionally have a front end, where the lively components reminiscent of transistors and capacitors are made, and a back end, which incorporates wires, called interconnects, and other metal connections that connect components of the chip.
However, some energy is lost in data transfer between these connections, and minor misalignments can affect performance. Stacking lively components would scale back the gap data has to travel and improve a chip's power efficiency.
Typically, it’s difficult to stack silicon transistors on a CMOS chip since the hot temperature required to fabricate additional devices on the front end would destroy the present transistors underneath.
MIT researchers turned this problem on its head and developed an integration technique to stack lively components on the back of the chip as an alternative.
“If we are able to use this back-end platform to include additional lively transistor layers slightly than simply interconnects, it might significantly increase the chip's integration density and improve its energy efficiency,” explains Shao.
The researchers achieved this using a brand new material, amorphous indium oxide, because the lively channel layer of their back-end transistor. The essential functions of the transistor happen within the lively channel layer.
Due to the unique properties of indium oxide, they will “grow” a particularly thin layer of this material on the back end of an existing circuit at a temperature of only about 150 degrees Celsius without damaging the device on the front end.
Perfect the method
They have fastidiously optimized the manufacturing process, minimizing the variety of defects in a layer of indium oxide material that is barely about 2 nanometers thick.
Some defects, called oxygen vacancies, are obligatory for the transistor to activate, but when there are too many defects it should not function properly. This optimized manufacturing process allows researchers to create a particularly small transistor that operates quickly and cleanly, eliminating much of the extra energy required to show a transistor on and off.
Building on this approach, additionally they made back-end transistors with integrated memory which are only about 20 nanometers in size. To do that, they added a fabric layer called ferroelectric hafnium-zirconium oxide as a storage component.
These compact memory transistors demonstrated switching speeds of just 10 nanoseconds, pushing the boundaries of the team's measurement instruments. This switching also requires a much lower voltage than comparable devices, reducing power consumption.
And since the memory transistors are so tiny, researchers can use them as a platform to check the basic physics of individual units of ferroelectric hafnium-zirconium oxide.
“If we understand the physics higher, we are able to use this material for a lot of latest applications. The energy consumption could be very low and it gives us numerous flexibility in designing devices. It could really open up many latest avenues for the long run,” says Shao.
The researchers also worked with a team on the University of Waterloo to develop a model of the performance of the back-end transistors. This is a crucial step before the devices might be integrated into larger circuits and electronic systems.
In the long run, they wish to construct on these demonstrations by integrating back-end memory transistors right into a single circuit. They also wish to improve the performance of the transistors and investigate how the properties of the ferroelectric hafnium-zirconium oxide might be controlled more precisely.
“Now we are able to construct a platform of versatile electronics on the backend of a chip, allowing us to realize high power efficiency and many alternative functionalities in very small devices. We have good device architecture and materials to work with, but we want to proceed innovating to uncover the final word performance limits,” says Shao.
This work is supported partly by Semiconductor Research Corporation (SRC) and Intel. Manufacturing took place on the MIT Microsystems Technology Laboratories and MIT.nano facilities.
